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Advanced Thin-Film Coatings for Through-Silicon Vias (TSV) and Through-Glass Vias (TGV)

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IC PACKAGING EVOLUTION: 
FROM WIRE BONDS TO GLASS INTERPOSERS

Every generation reduced interconnect length, increased I/O density, and boosted performance

Through-Silicon Vias (TSV) and Through-Glass Vias (TGV) are today’s frontiers

Packaging approach What it enables Where demand is
2.5D with TSV Ultra-bandwidth, low-latency links for 2.5D/3D AI/HPC, HBM on GPU/ASIC, networking
Panel glass with TGV Low-loss RF paths + panel-level scaling 5G/mmWave, radar, photonics/optics
Fan-Out (FO-WLP) Thin form factor, high-density RDL Mobile & edge AI (growing)
SiP / Heterogeneous Mix logic/RF/MEMS/power in one module IoT, automotive mid-tier (growing)
Flip-Chip Short interconnects, high I/O CPUs/SoCs (stable)
WLCSP Wafer-level, ultra-small footprint Sensors & small ICs (niche)
Wire Bonding Long wires, low I/O, low cost Legacy/cost-sensitive (mature)

TSV & TGV: The next leap in IC packaging

AI/HPC and 5G push interconnects into silicon and glass interposers, accelerating adoption of TSV and TGV across high-value programs. This shift concentrates performance and scale at the interposer, setting up the High-Aspect-Ratio Metallization challenges that coatings must solve next.

High-Aspect-Ratio (AR) Metallization Challenges

The Yield & Reliability Bottleneck

  • Critical Coating Requirements

    TSV and TGV manufacturing demand barrier, adhesion, and seed layers to be deposited uniformly.

  • Process
    Limitations

    Conventional approaches struggle with coverage, speed, and reliability in AR > 5:1 features.

  • Impact on Manufacturing Economics

    These limitations translate into yield loss, increased cost, and greater integration complexity.

The Critical Role of Coatings in TSV/TGV

Quality Requirements
Coatings must achieve 100% conformality in deep, narrow vias with high adhesion, low stress, and defect-free coverage.

Choosing the right route for superconformal deep-via barrier/seed

Comparing deposition routes for deep-via barrier/seed, FCVA uniquely combines high-AR via coverage, ion-bonded adhesion, pinhole-free density, and <100 °C deposition in one clean vacuum step.

Capability PVD (Sputtering) Electroless Plating ALD/CVD (Chemical Deposition) NTI Nanofilm FCVA
Step coverage in high-AR vias Limited (≈≤5:1) Good; repairs seed but low density ALD: excellent
CVD: better than PVD		 Excellent + dense in high AR
Adhesion to glass/silicon Moderate Variable (activation-dependent) Good with surface prep High (ion implantation, graded interface)
Film density & barrier quality Moderate Low–medium (NiP/Cu) ALD: high-density liners 
CVD: medium–high		 High, pinhole-free (ta-C ~3.3 g/cm³)
Deposition temperature Low (<200 °C) Low ALD: low–med (<200 °C) 
CVD: med–high (>300 °C)		 Low (<100 °C)
Throughput & thickness feasibility Fast for thin; struggles conformal thick Good rate; conformal; adds wet steps ALD: very slow >50 nm
CVD: moderate-fast		 High rate (thin–mid); single tool
Process complexity Often needs electroless repair Multi-bath + waste treatment Often paired with PVD/seed Single-step capable
Environmental footprint Low–medium High (wet chem waste) Low–medium (precursor/abatement) Low (dry vacuum)
Reliability under thermal cycling Thin-spot/seed delam risks Adhesion variability Good liners; stack-dependent Strong adhesion; dense barriers resist diffusion

Unlocking Performance, Yield, and Cost Advantages with FCVA

  • Environmental Compliance

    Vacuum process eliminates hazardous chemical waste.

  • Improved Vias Yield

    Reliable coverage in high-AR vias, reducing plating defects and rework.

  • Scalable Capability

    Wafer and potential panel-level readiness for high-volume production.

  • Process Simplification

    Reduced steps, faster throughput, lower total cost of ownership.

  • Enhanced Reliability

    Strong adhesion and barrier performance extend product lifespan.


FCVA Deposits Both Barrier and Seed Layers in High-AR Vias

Enables single-tool deposition of both barrier and seed layers, reducing process steps, improving yield.

  • Test Structure Containing 1 nm ta-C

  • X-TEM & ToF-SIMS confirms no Cu diffusion through 1 nm ta-C between Ti and SiO₂ after high-temp annealing at 600oC for 40 min

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